Digital Systems Testing And Testable Design Solution High Quality |work| -

The lab was a cathedral of silence, broken only by the whir of a $2-million Advantest T2000 tester. Jun pulled up the scan chain diagnostic on the main display. Red dots bloomed across a die map like a hemorrhaging vessel. Mode Switching: During normal operation

How Scan Works

1. Mode Switching: During normal operation, flip-flops (FFs) act as data registers. During test mode, they reconfigure into one or more long shift registers (scan chains).
2. Controllability: By shifting in a serial vector, any logic node can be set to 0 or 1.
3. Observability: After applying a test clock, the result is captured into FFs and shifted out for comparison.

• Testing: Manufacturing-based (finding faults in fabricated chips).
• Testable Design (DFT): Architectural techniques to make testing easier, cheaper, and faster.

2.2 Common Fault Models

| Fault Model | Description | Detection Method | |-------------|-------------|------------------| | Stuck-at (SA0/SA1) | Signal permanently 0 or 1 | Path sensitization | | Transition Delay | Signal fails to change fast enough | At-speed test | | Bridging | Short between two nodes | IDDQ or logic test | | Open | Disconnected net | Voltage/timing test | Mode Switching: During normal operation

• Goal: Test node (G) stuck-at-0.
• Step 1 (Sensitization): Drive (G=1) (D) via primary inputs.
• Step 2 (Propagation): Propagate D (good=1, faulty=0) to a primary output.
• Step 3 (Justification): Backward justify all signal assignments without conflict.

Rather than treating testing as an afterthought, DFT integrates features into the hardware specifically to facilitate testing. Common techniques include: Scan Design: Mode Switching: During normal operation