AM4 socket (also known as PGA 1331) uses a Pin Grid Array (PGA) layout where the pins are located on the processor package itself, fitting into 1,331 holes in the motherboard socket. Launched in 2016, it was AMD's first unified platform to support both high-end CPUs and APUs with integrated graphics on a single socket. Core Architecture and Specifications The AM4 layout is a square package measuring 40mm x 40mm
Missing Pin Indicators: Specific holes are plugged at the corners (13 pins) and near the center (8 pins) to ensure correct processor orientation during installation.
3. The "AM4 Mystery": Pin Configuration Variability
One of the most complex aspects of the AM4 layout is that not all 1,331 pins are utilized in the same way by every CPU. The pin map changes functionality depending on whether the processor has integrated graphics (APU) or is a discrete CPU.
3. Key Signal Groups
| Signal Type | Approx. Pin Count | Description | |-------------|------------------|-------------| | VDD (Core) | ~300 | Core voltage (~0.8–1.5V), distributed around the center | | VSS (Ground) | ~400 | Return current paths, interleaved with power | | VDDCR_SOC | ~60 | Uncore voltage (memory controller, Infinity Fabric, iGPU) | | VDDIO / VDD_MEM | ~40 | Memory I/O voltage (DDR4, 1.2V nominal) | | Infinity Fabric (IF) | ~80 | Differential pairs for chiplet-to-chiplet communication (IFIS) | | DDR4 Channels | ~240 | Two 64-bit channels (plus ECC), each with data, address, command, clock | | PCIe Gen 3/4 | ~200 | Up to 24 lanes (x16 GPU + x4 NVMe + x4 chipset) – each lane: TX+,TX-,RX+,RX- | | SATA / USB / GPIO | ~80 | Multiplexed with PCIe (FCH – Fusion Controller Hub) | | Clock & Reset | ~20 | 100 MHz BCLK, PWR_GOOD, RESET_L, SVI2 telemetry | | SVI2 bus | 2 pins | Serial Voltage Identification Interface 2 (voltage regulation control) | | Misc sense pins | ~10 | VDD_SENSE, VSS_SENSE (remote voltage sensing for VRM) |
Last updated: October 2025. Information compiled from AMD engineering white papers (NDA-broken), motherboard repair schematics, and the enthusiast community at r/AMDHelp.
